good
This commit is contained in:
Oscar
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/*
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instructions.h
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diStorm3 - Powerful disassembler for X86/AMD64
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http://ragestorm.net/distorm/
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distorm at gmail dot com
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Copyright (C) 2003-2021 Gil Dabah
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This library is licensed under the BSD license. See the file COPYING.
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*/
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#ifndef INSTRUCTIONS_H
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#define INSTRUCTIONS_H
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#include "config.h"
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#include "prefix.h"
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/*
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* Operand type possibilities:
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* Note "_FULL" suffix indicates to decode the operand as 16 bits or 32 bits depends on DecodeType -
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* actually, it depends on the decoding mode, unless there's an operand/address size prefix.
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* For example, the code: 33 c0 could be decoded/executed as XOR AX, AX or XOR EAX, EAX.
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*/
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typedef enum OpType {
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/* No operand is set */
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OT_NONE = 0,
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/* Read a byte(8 bits) immediate */
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OT_IMM8,
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/* Force a read of a word(16 bits) immediate, used by ret only */
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OT_IMM16,
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/* Read a word/dword immediate */
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OT_IMM_FULL,
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/* Read a double-word(32 bits) immediate */
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OT_IMM32,
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/* Read a signed extended byte(8 bits) immediate */
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OT_SEIMM8,
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/* Use a 8bit register */
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OT_REG8,
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/* Use a 16bit register */
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OT_REG16,
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/* Use a 16/32/64bit register */
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OT_REG_FULL,
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/* Use a 32bit register */
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OT_REG32,
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/*
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* If used with REX the reg operand size becomes 64 bits, otherwise 32 bits.
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* VMX instructions are promoted automatically without a REX prefix.
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*/
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OT_REG32_64,
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/* Use AL */
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OT_ACC8,
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/* Use AX (FSTSW) */
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OT_ACC16,
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/* Use AX/EAX/RAX */
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OT_ACC_FULL,
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/* Use AX/EAX, no REX is possible for RAX, used only with IN/OUT which don't support 64 bit registers */
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OT_ACC_FULL_NOT64,
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/* Read a byte(8 bits) immediate and calculate it relatively to the current offset of the instruction being decoded */
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OT_RELCB,
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/* Read a word/dword immediate and calculate it relatively to the current offset of the instruction being decoded */
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OT_RELC_FULL,
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/*
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* Instruction-Block for one byte long instructions, used by INC/DEC/PUSH/POP/XCHG,
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* REG is extracted from the value of opcode
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* Use a 8bit register
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*/
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OT_IB_RB,
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/* Use a 16/32/64bit register */
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OT_IB_R_FULL,
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/* Read an immediate as an absolute address, size is known by instruction, used by MOV (memory offset) only */
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OT_MOFFS8,
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OT_MOFFS_FULL,
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/* Use [(r)SI] as INDIRECTION, for repeatable instructions */
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OT_REGI_ESI,
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/* Use [(r)DI] as INDIRECTION, for repeatable instructions */
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OT_REGI_EDI,
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/* Use [(r)BX + AL] as INDIRECTIOM, used by XLAT only */
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OT_REGI_EBXAL,
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/* Use [(r)AX] as INDIRECTION, used by AMD's SVM instructions */
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OT_REGI_EAX,
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/* Use DX, as for OUTS DX, BYTE [SI] */
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OT_REGDX,
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/* Use ECX in INVLPGA instruction */
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OT_REGECX,
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/* FPU registers: */
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OT_FPU_SI, /* ST(i) */
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OT_FPU_SSI, /* ST(0), ST(i) */
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OT_FPU_SIS, /* ST(i), ST(0) */
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/* SSE registers: */
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OT_XMM,
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/* Extract the SSE register from the RM bits this time (used when the REG bits are used for opcode extension) */
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OT_XMM_RM,
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/* Implied XMM0 register as operand, used in SSE4. */
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OT_REGXMM0,
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/* Reg32/Reg 64 depends on prefix width only. */
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OT_WREG32_64,
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/* XMM is encoded in VEX.VVVV. */
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OT_VXMM,
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/* XMM is encoded in the high nibble of an immediate byte. */
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OT_XMM_IMM,
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/* YMM/XMM is dependent on VEX.L. */
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OT_YXMM,
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/* YMM/XMM (depends on prefix length) is encoded in the high nibble of an immediate byte. */
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OT_YXMM_IMM,
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/* YMM is encoded in reg. */
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OT_YMM,
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/* YMM is encoded in VEX.VVVV. */
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OT_VYMM,
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/* YMM/XMM is dependent on VEX.L, and encoded in VEX.VVVV. */
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OT_VYXMM,
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/* Use an immediate of 1, as for SHR R/M, 1 */
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OT_CONST1,
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/* Use CL, as for SHR R/M, CL */
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OT_REGCL,
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/* Use a control register */
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OT_CREG,
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/* Use a debug register */
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OT_DREG,
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/* Use a segment register */
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OT_SREG,
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/*
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* SEG is encoded in the flags of the opcode itself!
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* This is used for specific "push SS" where SS is a segment where
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* each "push SS" has an absolutely different opcode byte.
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* We need this to detect whether an operand size prefix is used.
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*/
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OT_SEG,
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/*
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* Special immediates for instructions which have more than one immediate,
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* which is an exception from standard instruction format.
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* As to version v1.0: ENTER, INSERTQ, EXTRQ are the only problematic ones.
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*/
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/* 16 bits immediate using the first imm-slot */
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OT_IMM16_1,
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/* 8 bits immediate using the first imm-slot */
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OT_IMM8_1,
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/* 8 bits immediate using the second imm-slot */
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OT_IMM8_2,
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/* Read one word (seg) and a word/dword/qword (depends on operand size), usually SEG:OFF, JMP 1234:1234 */
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OT_PTR16_FULL,
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/* Used only by MOV CR/DR(n). Promoted with REX onlly. */
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OT_FREG32_64_RM,
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/* MMX registers: */
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OT_MM,
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/* Extract the MMX register from the RM bits this time (used when the REG bits are used for opcode extension) */
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OT_MM_RM,
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/**** MEMORY only operands: ****/
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/* Use general memory indirection, with varying sizes: */
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OT_MEM,
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OT_MEM32,
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/* Memory dereference for MOVNTI, either 32 or 64 bits (with REX). */
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OT_MEM32_64,
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OT_MEM64,
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/* Used for cmpxchg8b/16b. */
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OT_MEM64_128,
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OT_MEM128,
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/*
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* Read one word (seg), and a word/dword/qword (depends on operand size) from memory.
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* JMP FAR [EBX] means EBX point to 16:32 ptr.
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*/
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OT_MEM16_FULL,
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/* Read one word (limit) and a dword/qword (limit) (depends on operand size), used by SGDT, SIDT, LGDT, LIDT. */
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OT_MEM16_3264,
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/* Used when a memory indirection is required, but if the mod field is 11, this operand will be ignored. */
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OT_MEM_OPT,
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/* Same as OT_RMXX but POINTS to 16 bits [cannot use GENERAL-PURPOSE REG!] */
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OT_FPUM16,
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/* Same as OT_RMXX but POINTS to 32 bits (single precision) [cannot use GENERAL-PURPOSE REG!] */
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OT_FPUM32,
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/* Same as OT_RMXX but POINTS to 64 bits (double precision) [cannot use GENERAL-PURPOSE REG!] */
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OT_FPUM64,
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/* Same as OT_RMXX but POINTS to 80 bits (extended precision) [cannot use GENERAL-PURPOSE REG!] */
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OT_FPUM80,
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/* Mem128/Mem256 is dependent on VEX.L. */
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OT_LMEM128_256,
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/**** MEMORY & REGISTER only operands: ****/
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/* Use or read (indirection) a 8bit register or immediate byte */
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OT_RM8,
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/* Some instructions force 16 bits (mov sreg, rm16) */
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OT_RM16,
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/* ModR/M for 32 bits. */
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OT_RM32,
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/*
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* Special operand type for MOV reg16/32/64/mem16, segReg 8C /r. and SMSW.
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* It supports all decoding modes, but if used as a memory indirection it's a 16 bit ModR/M indirection.
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*/
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OT_RFULL_M16,
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/* Use or read a 16/32/64bit register or immediate word/dword/qword */
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OT_RM_FULL,
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/* RM32/RM64 depends on prefix width only. */
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OT_WRM32_64,
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/*
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* Special type for SSE4, ModR/M might be a 32 bits or 64 bits (with REX) register or
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* a 8 bits memory indirection operand.
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*/
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OT_R32_64_M8,
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/*
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* Special type for SSE4, ModR/M might be a 32 bits or 64 bits (with REX) register or
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* a 16 bits memory indirection operand.
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*/
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OT_R32_64_M16,
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/*
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* 32 or 64 bits (with REX) operand size indirection memory operand.
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* Some instructions are promoted automatically without a REX prefix.
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*/
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OT_RM32_64,
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/* 16 or 32 bits RM. This is used only with MOVZXD instruction in 64bits. */
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OT_RM16_32,
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/*
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* Special operand type for SSE4 where the ModR/M might
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* be a 32 bits register or 8 bits memory indirection operand.
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*/
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OT_R32_M8,
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/*
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* Special ModR/M for PINSRW, which need a 16 bits memory operand or 32 bits register.
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* In 16 bits decoding mode R32 becomes R16, operand size cannot affect this.
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*/
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OT_R32_M16,
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/* Reg32/Reg64 (prefix width) or Mem8. */
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OT_REG32_64_M8,
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/* Reg32/Reg64 (prefix width) or Mem16. */
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OT_REG32_64_M16,
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/* ModR/M points to 32 bits MMX variable */
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OT_MM32,
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/* ModR/M points to 32 bits MMX variable */
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OT_MM64,
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/* ModR/M points to 16 bits SSE variable */
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OT_XMM16,
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/* ModR/M points to 32 bits SSE variable */
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OT_XMM32,
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/* ModR/M points to 64 bits SSE variable */
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OT_XMM64,
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/* ModR/M points to 128 bits SSE variable */
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OT_XMM128,
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/* AVX operands: */
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/* XMM or Mem32/Mem64 depends on perfix width only. */
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OT_WXMM32_64,
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/* YMM or Mem256. */
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OT_YMM256,
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/* YMM/XMM or Mem64/Mem256 is dependent on VEX.L. */
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OT_YXMM64_256,
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/* YMM/XMM or Mem128/Mem256 is dependent on VEX.L. */
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OT_YXMM128_256,
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/* XMM or Mem64/Mem256 is dependent on VEX.L. */
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OT_LXMM64_128
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} _OpType;
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/* Flags for instruction: */
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/* Empty flags indicator: */
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#define INST_FLAGS_NONE (0)
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/* The instruction we are going to decode requires ModR/M encoding. */
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#define INST_MODRM_REQUIRED (1)
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/* Special treatment for instructions which are in the divided-category but still needs the whole byte for ModR/M... */
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#define INST_NOT_DIVIDED (1 << 1)
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/*
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* Used explicitly in repeatable instructions,
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* which needs a suffix letter in their mnemonic to specify operation-size (depend on operands).
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*/
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#define INST_16BITS (1 << 2)
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/* If the opcode is supported by 80286 and upper models (16/32 bits). */
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#define INST_32BITS (1 << 3)
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/*
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* Prefix flags (6 types: lock/rep, seg override, addr-size, oper-size, REX, VEX)
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* There are several specific instructions that can follow LOCK prefix,
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* note that they must be using a memory operand form, otherwise they generate an exception.
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*/
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#define INST_PRE_LOCK (1 << 4)
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/* REPNZ prefix for string instructions only - means an instruction can follow it. */
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#define INST_PRE_REPNZ (1 << 5)
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/* REP prefix for string instructions only - means an instruction can follow it. */
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#define INST_PRE_REP (1 << 6)
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/* CS override prefix. */
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#define INST_PRE_CS (1 << 7)
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/* SS override prefix. */
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#define INST_PRE_SS (1 << 8)
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/* DS override prefix. */
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#define INST_PRE_DS (1 << 9)
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/* ES override prefix. */
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#define INST_PRE_ES (1 << 10)
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/* FS override prefix. Funky Segment :) */
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#define INST_PRE_FS (1 << 11)
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/* GS override prefix. Groovy Segment, of course not, duh ! */
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#define INST_PRE_GS (1 << 12)
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/* Switch operand size from 32 to 16 and vice versa. */
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#define INST_PRE_OP_SIZE (1 << 13)
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/* Switch address size from 32 to 16 and vice versa. */
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#define INST_PRE_ADDR_SIZE (1 << 14)
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/* Native instructions which needs suffix letter to indicate their operation-size (and don't depend on operands). */
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#define INST_NATIVE (1 << 15)
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/* Use extended mnemonic, means it's an _InstInfoEx structure, which contains another mnemonic for 32 bits specifically. */
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#define INST_USE_EXMNEMONIC (1 << 16)
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/* Use third operand, means it's an _InstInfoEx structure, which contains another operand for special instructions. */
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#define INST_USE_OP3 (1 << 17)
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/* Use fourth operand, means it's an _InstInfoEx structure, which contains another operand for special instructions. */
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#define INST_USE_OP4 (1 << 18)
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/* The instruction's mnemonic depends on the mod value of the ModR/M byte (mod=11, mod!=11). */
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#define INST_MNEMONIC_MODRM_BASED (1 << 19)
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/* The instruction uses a ModR/M byte which the MOD must be 11 (for registers operands only). */
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#define INST_MODRR_REQUIRED (1 << 20)
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/* The way of 3DNow! instructions are built, we have to handle their locating specially. Suffix imm8 tells which instruction it is. */
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#define INST_3DNOW_FETCH (1 << 21)
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/* The instruction needs two suffixes, one for the comparison type (imm8) and the second for its operation size indication (second mnemonic). */
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#define INST_PSEUDO_OPCODE (1 << 22)
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/* Invalid instruction at 64 bits decoding mode. */
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#define INST_INVALID_64BITS (1 << 23)
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/* Specific instruction can be promoted to 64 bits (without REX, it is promoted automatically). */
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#define INST_64BITS (1 << 24)
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/* Indicates the instruction must be REX prefixed in order to use 64 bits operands. */
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#define INST_PRE_REX (1 << 25)
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/* Third mnemonic is set. */
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#define INST_USE_EXMNEMONIC2 (1 << 26)
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/* Instruction is only valid in 64 bits decoding mode. */
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#define INST_64BITS_FETCH (1 << 27)
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/* Forces that the ModRM-REG/Opcode field will be 0. (For EXTRQ). */
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#define INST_FORCE_REG0 (1 << 28)
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/* Indicates that instruction is encoded with a VEX prefix. */
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#define INST_PRE_VEX (1 << 29)
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/* Indicates that the instruction is encoded with a ModRM byte (REG field specifically). */
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#define INST_MODRM_INCLUDED (1 << 30)
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/* Indicates that the first (/destination) operand of the instruction is writable. */
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#define INST_DST_WR (1 << 31)
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#define INST_PRE_REPS (INST_PRE_REPNZ | INST_PRE_REP)
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#define INST_PRE_LOKREP_MASK (INST_PRE_LOCK | INST_PRE_REPNZ | INST_PRE_REP)
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#define INST_PRE_SEGOVRD_MASK32 (INST_PRE_CS | INST_PRE_SS | INST_PRE_DS | INST_PRE_ES)
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#define INST_PRE_SEGOVRD_MASK64 (INST_PRE_FS | INST_PRE_GS)
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#define INST_PRE_SEGOVRD_MASK (INST_PRE_SEGOVRD_MASK32 | INST_PRE_SEGOVRD_MASK64)
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/* Extended flags for VEX: */
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||||
/* Indicates that the instruction might have VEX.L encoded. */
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#define INST_VEX_L (1)
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/* Indicates that the instruction might have VEX.W encoded. */
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#define INST_VEX_W (1 << 1)
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/* Indicates that the mnemonic of the instruction is based on the VEX.W bit. */
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#define INST_MNEMONIC_VEXW_BASED (1 << 2)
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||||
/* Indicates that the mnemonic of the instruction is based on the VEX.L bit. */
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#define INST_MNEMONIC_VEXL_BASED (1 << 3)
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/* Forces the instruction to be encoded with VEX.L, otherwise it's undefined. */
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#define INST_FORCE_VEXL (1 << 4)
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/*
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* Indicates that the instruction is based on the MOD field of the ModRM byte.
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* (MOD==11: got the right instruction, else skip +4 in prefixed table for the correct instruction).
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||||
*/
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#define INST_MODRR_BASED (1 << 5)
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/* Indicates that the instruction doesn't use the VVVV field of the VEX prefix, if it does then it's undecodable. */
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#define INST_VEX_V_UNUSED (1 << 6)
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||||
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||||
/* Indication that the instruction is privileged (Ring 0), this should be checked on the opcodeId field. */
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#define META_INST_PRIVILEGED ((uint16_t)0x8000)
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||||
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||||
/*
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||||
* Indicates which operand is being decoded.
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||||
* Destination (1st), Source (2nd), op3 (3rd), op4 (4th).
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||||
* Used to set the operands' fields in the _DInst structure!
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||||
*/
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||||
typedef enum {ONT_NONE = -1, ONT_1 = 0, ONT_2 = 1, ONT_3 = 2, ONT_4 = 3} _OperandNumberType;
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||||
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||||
/* CPU Flags that instructions modify, test or undefine, in compacted form (CF,PF,AF,ZF,SF are 1:1 map to EFLAGS). */
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||||
#define D_COMPACT_CF 1 /* Carry */
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||||
#define D_COMPACT_PF 4 /* Parity */
|
||||
#define D_COMPACT_AF 0x10 /* Auxiliary */
|
||||
#define D_COMPACT_ZF 0x40 /* Zero */
|
||||
#define D_COMPACT_SF 0x80 /* Sign */
|
||||
/* The following flags have to be translated to EFLAGS. */
|
||||
#define D_COMPACT_IF 2 /* Interrupt */
|
||||
#define D_COMPACT_DF 8 /* Direction */
|
||||
#define D_COMPACT_OF 0x20 /* Overflow */
|
||||
|
||||
/* The mask of flags that are already compatible with EFLAGS. */
|
||||
#define D_COMPACT_SAME_FLAGS (D_COMPACT_CF | D_COMPACT_PF | D_COMPACT_AF | D_COMPACT_ZF | D_COMPACT_SF)
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||||
|
||||
/*
|
||||
* In order to save more space for storing the DB statically,
|
||||
* I came up with another level of shared info.
|
||||
* Because I saw that most of the information that instructions use repeats itself.
|
||||
*
|
||||
* Info about the instruction, source/dest types, meta and flags.
|
||||
* _InstInfo points to a table of _InstSharedInfo.
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t flagsIndex; /* An index into FlagsTables */
|
||||
uint8_t s, d; /* OpType. */
|
||||
/*
|
||||
* The following are CPU flag masks that the instruction changes.
|
||||
* The flags are compacted so 8 bits representation is enough.
|
||||
* They will be expanded in runtime to be compatible to EFLAGS.
|
||||
*/
|
||||
uint8_t modifiedFlagsMask;
|
||||
uint8_t testedFlagsMask;
|
||||
uint8_t undefinedFlagsMask;
|
||||
uint16_t meta; /* High byte = Instruction set class | Low byte = flow control flags. */
|
||||
} _InstSharedInfo;
|
||||
|
||||
/*
|
||||
* This structure is used for the instructions DB and NOT for the disassembled result code!
|
||||
* This is the BASE structure, there are extensions to this structure below.
|
||||
*/
|
||||
typedef struct {
|
||||
uint16_t sharedIndex; /* An index into the SharedInfoTable. */
|
||||
uint16_t opcodeId; /* The opcodeId is really a byte-offset into the mnemonics table. MSB is a privileged indication. */
|
||||
} _InstInfo;
|
||||
|
||||
/*
|
||||
* There are merely few instructions which need a second mnemonic for 32 bits.
|
||||
* Or a third for 64 bits. Therefore sometimes the second mnemonic is empty but not the third.
|
||||
* In all decoding modes the first mnemonic is the default.
|
||||
* A flag will indicate it uses another mnemonic.
|
||||
*
|
||||
* There are a couple of (SSE4) instructions in the whole DB which need both op3 and 3rd mnemonic for 64bits,
|
||||
* therefore, I decided to make the extended structure contain all extra info in the same structure.
|
||||
* There are a few instructions (SHLD/SHRD/IMUL and SSE too) which use third operand (or a fourth).
|
||||
* A flag will indicate it uses a third/fourth operand.
|
||||
*/
|
||||
typedef struct {
|
||||
/* Base structure (doesn't get accessed directly from code). */
|
||||
_InstInfo BASE;
|
||||
|
||||
/* Extended starts here. */
|
||||
uint8_t flagsEx; /* 8 bits are enough, in the future we might make it a bigger integer. */
|
||||
uint8_t op3, op4; /* OpType. */
|
||||
uint16_t opcodeId2, opcodeId3;
|
||||
} _InstInfoEx;
|
||||
|
||||
/* Trie data structure node type: */
|
||||
typedef enum {
|
||||
INT_NOTEXISTS = 0, /* Not exists. */
|
||||
INT_INFO = 1, /* It's an instruction info. */
|
||||
INT_INFOEX,
|
||||
INT_INFO_TREAT, /* Extra intervention is required by inst_lookup. */
|
||||
INT_LIST_GROUP,
|
||||
INT_LIST_FULL,
|
||||
INT_LIST_DIVIDED,
|
||||
INT_LIST_PREFIXED
|
||||
} _InstNodeType;
|
||||
|
||||
/* Used to check instType < INT_INFOS, means we got an inst-info. Cause it has to be only one of them. */
|
||||
#define INT_INFOS (INT_LIST_GROUP)
|
||||
|
||||
/* Instruction node is treated as { int index:13; int type:3; } */
|
||||
typedef uint16_t _InstNode;
|
||||
|
||||
_InstInfo* inst_lookup(_CodeInfo* ci, _PrefixState* ps, int* isPrefixed);
|
||||
_InstInfo* inst_lookup_3dnow(_CodeInfo* ci);
|
||||
|
||||
#endif /* INSTRUCTIONS_H */
|
||||
|
||||
Reference in New Issue
Block a user